How to write an adaptive macro

The Keil assembler has eight 8 bit registers which can
be alternatively used in some versions of the 8051 as
four 16 bit registers or even two 32 bit registers:

8 bit: R0, R1, R2, R3, R4, R5, R6, R7
16 bit: WR0=R0:R1 WR2=R2:R3 WR4=R4:R5 WR6=R6:R7
32 BIR: DR0=R0:R1:R2:R3  DR4=R4:R5:R6:R7

I would like to write some macros to ease the usage of
the WRx and DRx register combinations. If the argument
is WR4, a sequence of instructions like..

ADD  .. R5
ADDC .. R4

and if the argument is DR0, instructions like..

ADD  .. R3
ADDC .. R2
ADDC .. R1
ADDC .. R0

shall get generated. How can this be done in an easy
way with the Intel macro language?

On Fri, 26 May 2006 18:21:11 +0200, "PMH"  <spamtrap@crayne.org> wrote
in comp.lang.asm.x86:

> The Keil assembler has eight 8 bit registers which can
> be alternatively used in some versions of the 8051 as
> four 16 bit registers or even two 32 bit registers:
>
>  8 bit: R0, R1, R2, R3, R4, R5, R6, R7
> 16 bit: WR0=R0:R1 WR2=R2:R3 WR4=R4:R5 WR6=R6:R7
> 32 BIR: DR0=R0:R1:R2:R3  DR4=R4:R5:R6:R7
>
> I would like to write some macros to ease the usage of
> the WRx and DRx register combinations. If the argument
> is WR4, a sequence of instructions like..
>
> ADD  .. R5
> ADDC .. R4
>
> and if the argument is DR0, instructions like..
>
> ADD  .. R3
> ADDC .. R2
> ADDC .. R1
> ADDC .. R0
>
> shall get generated. How can this be done in an easy
> way with the Intel macro language?

This group only supports assembly language for PC compatible
processors, namely the x86 line, from Intel and others.  The 8051 is
most definitely not a PC compatible processor.

As for what "Intel macro language" might be, I haven't got the
faintest idea.

The place to ask about 8051 controllers and Keil tools is
news:comp.arch.embedded.

--
Jack Klein
Home: http://JK-Technology.Com
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http://www.contrib.andrew.cmu.edu/~.../FAQ-acllc.html

Thank you for the comp.arch.embedded advise. I had not found it.

Intel's "Macro Processing Language" should be almost identical
on the C51 and x86 assemblers.

PMH