lex/yacc and verilog

Hi all,

I'm new to this forum and need some help with lex/yacc.  

I'm writing a parser that takes a verilog module specification I've develope
d as an input.

My question might seem relatively simple to this group since my job function
 is not software development.  My main problem is that I can't figure out wh
ere to place a sensible boundary between lex and yacc.

The verilog signal specification we've developed can take the form of:

[code]
variable = 0 to 10;
SIGNAL storage_{variable}_ack[12:0]
SIGNAL storage_req
SIGNAL storage_buffer[12:0]
[\code]

How do I write a lexer that takes into account all of these formats, and mor
e importantly, how do I then store the bit range values and the variable ref
erences and associate them with the signal?

For now I've written complex grammar rules in yacc to account for each uniqu
e combination:

[code] 
STRING '[' INT ':' INT ']'
STRING '{' STRING '}' STRING '[' INT ':' INT ']'
[\code]
etc etc etc...

It's easy to observe that the grammar rules quickly become unmanageable at s
ome point and that the tool will not scale easily as multiple variables can 
be referenced...

It seems obvious to me that this bit-range/variable parsing needs to be done
 initially in the lexer, and then the entire signal structure passed to yacc
..  I'm just not sure how to do this in lex.  This would be a cakewalk in s
omething like PERL, but lex cannot grab "pieces" of a regular expression mat
ch... or at least I'm not aware of it.

Can someone help?

Signed,
hardware architect in dire need of good software experience