How to specify the dependence between hearder files?

Hi,

Suppose, I have the following files.

main.cc fun.cc
main.h main1.h fun.h
debug.h

The first type dependence: Each .o file depends on its correspondent
.cc and .h file. In addition main.o also depends on main1.h
The second type dependence: main1.h file include debug.h, so if debug.h
changes, main.o, which is depend on main1.h, should also change.(I know
I can write main.o: debug.h, but main.o doesn't directly depend on
debug.h)

The following is the incorrect makefile, which can not reflect the
second dependence. Would you please tell me how to do it? Thanks.

Best wishes,
Peng

%.o:    %.cc %.h
$(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $<

main.o: main1.h

main1.h: debug.h

<PengYu.UT@gmail.com> wrote in message
news:1113685664.558313.142350@z14g2000cwz.googlegroups.com...
> Hi,
>
> Suppose, I have the following files.
>
> main.cc fun.cc
> main.h main1.h fun.h
> debug.h
>
> The first type dependence: Each .o file depends on its correspondent
> .cc and .h file. In addition main.o also depends on main1.h
> The second type dependence: main1.h file include debug.h, so if debug.h
> changes, main.o, which is depend on main1.h, should also change.(I know
> I can write main.o: debug.h, but main.o doesn't directly depend on
> debug.h)
>
> The following is the incorrect makefile, which can not reflect the
> second dependence. Would you please tell me how to do it? Thanks.
>
> Best wishes,
> Peng
>
> %.o:    %.cc %.h
>        $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $<
>
> main.o: main1.h
>
> main1.h: debug.h

The usual solution is to create a dependency file that holds the
depedencies between .c and .h files. The compiler can make the dependency
file. Try adding these lines to your makefile:

.dep:
$(CXX) -M $(CPPFLAGS) $(CXXFLAGS) main.cc fun.cc > .dep

include .dep

DS

Do you mean that I have to run "make .dep" before I run "make"? How can
I write makefile in a way such that I can simply type "make"?

The following is my makefile.

Best wishes,
Peng

#########makefile
.PHONY: all clean
SHELL = /bin/bash
OBJS = $(patsubst %.cc,%.o,$(wildcard *.cc))
TARGET = main
LIBS = -lfftw3
CXXFLAGS = -g #-O3
CXX = g++-3.3
CC = g++-3.3
LAPACKINC = /usr/local/include/clapack/
LAPACKLIB = /home/polaris/yupeng/lapacklib/
CBLASLIB = /usr/lib/sse2/
CXXFLAGS := $(CXXFLAGS) -I$(LAPACKINC)
LDLIBS = -L$(LAPACKLIB) -ltmg -llapack -lblas
-L/usr/src/clapack/CLAPACK/F2CLIBS/ -lF77 -lI77 -L$(
CBLASLIB) -lcblas -latlas -lm -lc -lfftw3


all:    $(TARGET)

$(TARGET):      $(OBJS)

include .dep

.dep:
$(CXX) -MM $(CPPFLAGS) $(CXXFLAGS) $(wildcard *.cc) > .dep

clean:
@$(RM) *.o $(TARGET) core

Hi Peng,

If you are using GNU make and gcc, look up "Generating Prerequisites
Automatically" in the make info and "Options Controlling the
Preprocessor" in the gcc info, i.e.

$ info make "Automatic Prerequisites"
$ info gcc "Invoking GCC" "Preprocessor Options"

I normally end up with something like this:

CC_SRCS=main.cc x.cc y.cc z.cc

DEPENDS=$(addsuffix .d,$(basename $(CC_SRCS)))

%.d: %.cc
g++ -MM -MG -MT $@ -MT $(<:%.cc=%.o) $(INC_FLAGS) -o $@ $<

-include $(DEPENDS)


--Phil

<PengYu.UT@gmail.com> wrote in message
news:1113692216.009576.247970@o13g2000cwo.googlegroups.com...

> Do you mean that I have to run "make .dep" before I run "make"? How can
> I write makefile in a way such that I can simply type "make"?

No, you don't. You included '.dep', so your makefile depends on it. Make
will make dependencies, that's its whole purpose.

> The following is my makefile.
[snip]

It looks okay. What problems are you still having?

DS