makefile woes

Hi folks,

I am having some trouble getting a makefile to work in the way I need it
to.  It involves building a header file dependency list using the gcc
-MM feature, but either it's not always being made when it needs to be,
or it is made every time even when it isn't needed (or even desired, for
targets like clean, for instance).

I've tried various combinations of:
1) marking it .PHONY
2) setting it a prerequisite for the object files
3) giving it the .c files as prerequisites
...all to no avail.

One problem seems to be that I can't find a way of conditionally
including it only for the targets the require those dependencies to be
listed in the makefile (namely the object files).  make clean and
friends obviously have no need for this file (make clean removes it
even) and as such its absence *should* not cause any trouble.

The other problem is that I can't seem to ensure it gets built only when
it needs to be, without making it being unconditionally.

I'm fumbling around in the dark here, as the info pages are not very
helpful and google hasn't turned up much either.  The suggested solution
in the info page (writing a separate makefile for each source file)
seems far from optimal and I've never seen this technique used in practice.

What are other people doing?

Thanks in advance,
Koster

T Koster wrote:
> Hi folks,
>
> I am having some trouble getting a makefile to work in the way I need it
> to.  It involves building a header file dependency list using the gcc
> -MM feature, but either it's not always being made when it needs to be,
> or it is made every time even when it isn't needed (or even desired, for
> targets like clean, for instance).
>
> I've tried various combinations of:
>     1) marking it .PHONY
>     2) setting it a prerequisite for the object files
>     3) giving it the .c files as prerequisites
> ...all to no avail.

I have sone somthing similar in MakeXS.  MakeXS is just a huge Makefile
(to the first approximation).

>
> One problem seems to be that I can't find a way of conditionally
> including it only for the targets the require those dependencies to be
> listed in the makefile (namely the object files).  make clean and
> friends obviously have no need for this file (make clean removes it
> even) and as such its absence *should* not cause any trouble.
>
> The other problem is that I can't seem to ensure it gets built only when
> it needs to be, without making it being unconditionally.

You only need to include it if it exists. (hint)

>
> I'm fumbling around in the dark here, as the info pages are not very
> helpful and google hasn't turned up much either.  The suggested solution
> in the info page (writing a separate makefile for each source file)
> seems far from optimal and I've never seen this technique used in practice.[/color
]

I'm actually considering adding a per source Makefile that can be used
to tailor compilation of each source (if needed).  I have not needed to
do this yet.

>
> What are other people doing?

MakeXS does this.  See if the strategy I employed there works for you.

www.makexs.com