req: help w/ makefile

Greetings,
I'm having a problem with my makefile.  It seems to not do a variable
substition for a prerequisite where I need it to happen.
See makefile below.  The problem occurs when I try to do this:
make buildall
I think it should try to build all dlls listed in the variable
dllfiles.  It does nothing instead.
I ran this with the -p option and the output shows no prerequisites for
buildall:

If I do "make component=shmem"
it works wonderfully.

What gives?
TIA,
Dave

This is a extreme simplification of my actual makefile, but still
displays the behavior described.

############### top of makefile ##############
.IGNORE:
.SUFFIXES: .mak .lib .dll

MAKEFILE = makefile
platform = linux
PLATFORM_CODE = LX

 ########################################
##
#
#   The assumption for this file is that
#   <component>$(PLATFORM_CODE)
#   is the name of the make file.
#
 ########################################
###
$(component) : $(component)$(PLATFORM_CODE).dll

buildall     : $(dllfiles)
@echo "Building all lib and shared lib targets"


dllfiles  = shmem$(PLATFORM_CODE).dll	\
sembb$(PLATFORM_CODE).dll

 ########################################
#######             #
#   Inference rules
#
 ########################################
#######
.mak.dll:
@echo "*********************************"
@echo "*********************************"
@echo Building $*.mak file
@$(COPY) BBVersionInfo.h productverinfo.h
@$(MAKE) -f $*.mak platform=$(platform) LIBTYPE=dll  all
############## end of makefile #################

"kaatzd@hotmail.com" wrote:
>
> Greetings,
> I'm having a problem with my makefile.  It seems to not do a variable
> substition for a prerequisite where I need it to happen.
> See makefile below.  The problem occurs when I try to do this:
> make buildall
> I think it should try to build all dlls listed in the variable
> dllfiles.  It does nothing instead.
> I ran this with the -p option and the output shows no prerequisites for
> buildall:
>
> If I do "make component=shmem"
> it works wonderfully.
>
> What gives?
> TIA,
> Dave
>
> This is a extreme simplification of my actual makefile, but still
> displays the behavior described.
>
> ############### top of makefile ##############
> .IGNORE:
> .SUFFIXES: .mak .lib .dll
>
> MAKEFILE = makefile
> platform = linux
> PLATFORM_CODE = LX
>
>  ########################################
##
> #
> #   The assumption for this file is that
> #   <component>$(PLATFORM_CODE)
> #   is the name of the make file.
> #
>  ########################################
###
> $(component) : $(component)$(PLATFORM_CODE).dll
>
> buildall     : $(dllfiles)
> @echo "Building all lib and shared lib targets"

At this point, "dllfiles" is not defined, so $(dllfiles) expands to
nothing. Move the definition of dllfiles so it appears above the
buildall line. Also, note that you must have a tab in front of the @echo
command or make will complain about "no separator".


>
> dllfiles  = shmem$(PLATFORM_CODE).dll   \
> sembb$(PLATFORM_CODE).dll
>
>  ########################################
#######             #
> #   Inference rules
> #
>  ########################################
#######
> .mak.dll:
> @echo "*********************************"
> @echo "*********************************"
> @echo Building $*.mak file
> @$(COPY) BBVersionInfo.h productverinfo.h
> @$(MAKE) -f $*.mak platform=$(platform) LIBTYPE=dll  all
> ############## end of makefile #################

--
Fred L. Kleinschmidt
Boeing Associate Technical Fellow
Technical Architect, Common User Interface Services
M/S 2R-94  (206)544-5225

I thought I already replied to this - sorry if it shows up twice.
Thanks Fred,
Indeed you are correct, and I feel foolish for asking.  I thought I had
tried moving the variable assignment of dllfiles above, or the buildall
rule below, but apparently didn't do that.
Thanks again,
Dave