Home > Archive > VHDL > October 2005 > Looking for AES (Rijndael) model for verification
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Looking for AES (Rijndael) model for verification
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| Hello,
I need to model the behavior of the AES (Rijndael) algoritm for
encryption and decryption (128 bit). A model in C, Verilog, VHDL, or
Vera would be fine. Anybody have something like this that they'd like
to share?
Thanks.
--
Marty
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| Hi Marty,
There are a number of free AES cores on the web (opencores.org, my website).
The validation is quite straightforward and consist of iterating the core
400*10000 time and comparing the output results against published data
(simple textfile compare). Have a look at the testbench in
http://www.ht-lab.com/freecores/AES/aes.html, the output is the same as the
published data. The only di vantage is that the full RTL test takes nearly
11 hours on my AMD3500+.
Hans.
www.ht-lab.com
"Marty" <m_piet@yahoo.com> wrote in message
news:1130359474.480772.179340@z14g2000cwz.googlegroups.com...
> Hello,
>
> I need to model the behavior of the AES (Rijndael) algoritm for
> encryption and decryption (128 bit). A model in C, Verilog, VHDL, or
> Vera would be fine. Anybody have something like this that they'd like
> to share?
>
> Thanks.
> --
> Marty
>
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