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| Nathaniel 2005-10-08, 9:58 pm |
| hey,
I am doing a pretty  project using processors working on different
clock domains on the same FPGA. For com purposes, i need an async fifo,
but i cannot use the logic Core fifo's from xilinx or altera, we wan
the design platform-independant. Is there any good source code in
VHDL/Verilog for an asynchronous FIFO?
Nathaniel
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| vizziee@gmail.com 2005-10-10, 3:58 am |
| >> asynchronous FIFO?
Do you mean a FIFO with asynchronous clear or a FIFO with
unsynchronized read and write clocks?
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| Nathaniel 2005-10-10, 7:04 pm |
| a FIFO with async read and write clocks
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| ALuPin@web.de 2005-10-11, 8:00 am |
| There is some example shown on
"www.vhdl-online.de"
model lib patras.
Haven't tested it but have a look at it. Maybe some inspiration ...
Rgds
Andr=E9
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| Nathaniel 2005-10-23, 7:01 pm |
| thanks a milion
i'll check to see if it's half decent and report back
NA
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