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Author Please help us in understanding motion JPEG2000
hswnetin

2005-03-11, 3:55 am

Hi All,

We are working on implementation of Motion JPEG2000 on FPGA.

Specifications for encoder as follows,

1. 30 frames/sec
2. Image size 1024x1024 (RGB)
3. RGB of 12-bits each
4. System clock = 50MHz

The input is also 30 frames/sec.

The most efficient bit plane coder architecture, takes NxNx16x3 clock
cycles.
Where NxN is code block size. Number 16 indicates number of bit planes
and 3 indicates number of passes for each bit plane.

If N=512, number of clocks required to complete one band is
512x512x16x3 = 1,25,82,912. Assuming one level of DWT and parallel
processing of four bands, we get frame rate of 1fps (frame per sec).
How to achieve 30 fps?

Please help us.

Thx and rgds,
hswnetin
Thomas Richter

2005-03-11, 3:55 pm

hswnetin wrote:

> Specifications for encoder as follows,
>
> 1. 30 frames/sec
> 2. Image size 1024x1024 (RGB)
> 3. RGB of 12-bits each


Cinematic profile of JPEG2000? (-;

> 4. System clock = 50MHz
>
> The input is also 30 frames/sec.
>
> The most efficient bit plane coder architecture, takes NxNx16x3 clock
> cycles.


No, wrong. Who says that you have to encode all bitplanes? You only have
to encode as many as you need to get your desired target quality. These
are definitely less than 16.

> Where NxN is code block size. Number 16 indicates number of bit planes
> and 3 indicates number of passes for each bit plane.
>
> If N=512,


The cinematic profile uses 32x32 codeblocks, thus 1024 coefficients per
codeblock.

> number of clocks required to complete one band is
> 512x512x16x3 = 1,25,82,912. Assuming one level of DWT and parallel
> processing of four bands, we get frame rate of 1fps (frame per sec).
> How to achieve 30 fps?


Simple: Not with that hardware. By not encoding some bitplanes, you can
get it faster by possibly a factor of four. You will not archive 30fps
with *that* hardware. Plain and simple. Thus, tell your management. (-;


So long,
Thomas
moogie

2005-03-12, 3:55 am

hswnetin@yahoo.com (hswnetin) wrote in message news:<a4d4dd49.0503102224.6f86e709@posting.google.com>...
> Hi All,
>
> We are working on implementation of Motion JPEG2000 on FPGA.
>
> Specifications for encoder as follows,
>
> 1. 30 frames/sec
> 2. Image size 1024x1024 (RGB)
> 3. RGB of 12-bits each
> 4. System clock = 50MHz
>
> The input is also 30 frames/sec.
>
> The most efficient bit plane coder architecture, takes NxNx16x3 clock
> cycles.
> Where NxN is code block size. Number 16 indicates number of bit planes
> and 3 indicates number of passes for each bit plane.
>
> If N=512, number of clocks required to complete one band is
> 512x512x16x3 = 1,25,82,912. Assuming one level of DWT and parallel
> processing of four bands, we get frame rate of 1fps (frame per sec).
> How to achieve 30 fps?
>
> Please help us.
>
> Thx and rgds,
> hswnetin



While i am not very knowledgable about FPGAs, i do know that they are
are massively paralell.

Thus is seems reasonable to perform DCT on each 8x8 block of the image
simultaneously (or as much as is able to be done in parallel on the
FPGA you are using)
hswnetin

2005-03-24, 3:55 am

Hi All,

We thank the group and the group members. Our special thanks to Thomas
Richter and moogie. As you said we are thinking of coding the bit
planes which are necessary. We are doing the ground work to achieve
the specifications. For further clarifications we will consults you.
Thanks again.

Regards,
hswnetin


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