| multicsfan 2006-01-17, 6:56 pm |
| Well those options were in the proposal Cray sent to RPI around
1974/1975 when RPI was looking to replace their old 360-50. Those
numbers came from the Cray proposal. It is possible that at the time of
the proposal those were options and later things changed. I don'tknow
how many Cray's had been delivered at that time. Around 1976/1977 the
RPI-ACM had a guest lecturer from a site with a Cray or had worked at a
site with a Cray. The comment I remember most was the MTBF was about 4
hours and the MTTR was about 10 minutes (the time to wiggle all the boards).
Dan Nagle wrote:
> Hello,
>
> multicsfan wrote:
>
> <snip>
>
>
>
> No Cray-1 ever had hardware divide.
> Floating point divide was always a reciprocal approximation,
> followed by correcting multiplications. A special 2-a.b instruction
> applied part of the correction.
>
>
>
> Serial #1 Cray-1 had no parity, Serial #2 was being built without parity
> but was scrapped before completion. Serials #3 and beyond
> all had SECDED. It added one clock to scalar memory fetch times,
> raising it from 10 to 11 cp.
>
> The only options ever available on the Cray-1 was how much memory
> the customer wanted to buy. (Modulo peripherals, of course.)
> Most were sold with 1 MW, from 256 KW to 4 MW was
> theoretically possible.
>
|