ASM370 - Assembler "TRE" Instruction

Author

Assembler "TRE" Instruction

wobconsult

2005-03-14, 3:55 am

I'm trying to get the correct syntax for an ASSEMBER "TRANSLATE
EXTENDED" ( TRE ) instruction. It looks like it can be used to
translate ( TR ) more that 256-bytes at a time. Although it's defined
to "POPS", it's one of those newer "RRE" formats, which I've never
used.

Does anyone have a "working" example? Would be most appreciated.

Thanks....

Andreas Lerch

2005-03-14, 3:55 pm

Am 14.03.05, 06:52:17, schrieb "wobconsult" <wobconsult@sprynet.com> zum=
=20
Thema Assembler "TRE" Instruction:

[color=darkred]
> I'm trying to get the correct syntax for an ASSEMBER "TRANSLATE
> EXTENDED" ( TRE ) instruction. It looks like it can be used to
> translate ( TR ) more that 256-bytes at a time. Although it's defined=

> to "POPS", it's one of those newer "RRE" formats, which I've never
> used.

> Does anyone have a "working" example? Would be most appreciated.

Hello

have you read this=20
http://publibfp.boulder.ibm.com/cgi...dz9zr003/7.5.14
4?SHELF=3D&DT=3D20040504121320

you can find it here:

Title: z/Architecture Principles of Operation
Document Number: SA22-7832-03
Build Date: 05/04/04 12:13:20 Build Version: 1.3.1 of BUILD/VM=20
Version: UG03935 DropDate: Thursday August 8, 2003
Book Path: /home/webapps/epubs/htdocs/book/dz9zr003.boo=20

and this is the trick:
The R1 field designates an even-odd pair of general registers and=20
must designate an even-numbered register; otherwise, a specification=20=

exception is recognized.

Einen schoenen Tag
Andreas Lerch

wobconsult

2005-03-14, 8:55 pm

Andreas,

So, it sort of resembles an MVCL (format RR).

Let's say I have the following -

LA R0,TRNSAREA
L R1,=3DA(L'TRNSAREA)
LA R14,TRNSTBL
LA R15,L'TRNSTBL

TRE R0,R14

With TRNSAREA being the area to translate and TRNSTBL being the
256-byte Translate-Tbl.

I'm pretty sure R1 is being loaded correctly, but I'm not sure about
R15.

Does this look OK to you?

Thanks....

Andreas Lerch wrote:
>
> Am 14.03.05, 06:52:17, schrieb "wobconsult" <wobconsult@sprynet.com>
zum
> Thema Assembler "TRE" Instruction:
>
>
defined[color=darkred]
>
>
> Hello
>
> have you read this
> http://publibfp.boulder.ibm.com/cgi...dz9zr003/7.5.14
> 4?SHELF=3D&DT=3D20040504121320
>
> you can find it here:
>
> Title: z/Architecture Principles of Operation
> Document Number: SA22-7832-03
> Build Date: 05/04/04 12:13:20 Build Version: 1.3.1 of BUILD/VM
> Version: UG03935 DropDate: Thursday August 8, 2003
> Book Path: /home/webapps/epubs/htdocs/book/dz9zr003.boo
>
> and this is the trick:
> The R1 field designates an even-odd pair of general registers and
> must designate an even-numbered register; otherwise, a specification
> exception is recognized.
>=20
> Einen schoenen Tag
> Andreas Lerch

glen herrmannsfeldt

2005-03-15, 8:55 am

wobconsult wrote:
> Andreas,
>
> So, it sort of resembles an MVCL (format RR).
>
> Let's say I have the following -
>
> LA R0,TRNSAREA
> L R1,=A(L'TRNSAREA)
> LA R14,TRNSTBL
> LA R15,L'TRNSTBL
>
> TRE R0,R14
>
> With TRNSAREA being the area to translate and TRNSTBL being the
> 256-byte Translate-Tbl.

It specifically says that neither R1 or R2, should be zero, as
register 0 is used directly by the instruction. (I believe that
means it shouldn't be register 0, not that the contents shouldn't be
zero.) Also, as with all translate instructions the length of the
table is not needed. R2+1 is not used.

-- glen

wobconsult

2005-03-15, 3:55 pm

Glenn,

I'm going to use R8/R9 (which comprises "R1") and R10 ("R2+0") which
contains the translate-tbl address. R11 ("R2+1") will contain X'00's.

TRE R8,R10

Unfortunately, I have no way of testing this at the moment.

Thanks....

wobconsult

2005-03-19, 3:55 pm

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